As the value and use of information continues to increase, individuals and businesses continually seek additional ways to process and store information. One option available to users of information is an information handling system. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems, including computer systems, may be designed to conform with one or more industry specifications for managing power consumption in a computer system. One of those industry specifications is the Advanced Configuration and Power Interface (ACPI) specification. The ACPI specification establishes common interfaces and controls for managing power consumption and the configuration of a computer system and the devices of the computer system.
The ACPI specification includes a provision for two General-Purpose Event Register Blocks for tracking power events and configuration events in the computer system. For the purposes of this disclosure, power events and configuration events may be referred to generally as system events. Each of the General-Purpose Event Register Blocks includes two registers, an enable register and a status register. The registers are typically included in the chip set of the computer system. In one implementation, the registers may be included, for example, in the I/O Controller Hub (ICH) of the Intel Hub Architecture or as part of a separate embedded controller. Each register will include an input pin or inputs pins for providing an input to the register to signal various power events in the computer system. Each bit in the status of a General-Purpose Event Register Block corresponds to an enable bit that has the same bit position in the enable register of the General-Purpose Event Register Block. When an enable bit is set, a set status bit in the corresponding bit position in the status register will set a bit that initiates a system control interrupt (SCI). Thus, when a system event occurs—such as the insertion of a drive, or the activation of a keyboard or mouse—the status bit associated with the system event will be set. If a corresponding enable bit is set, a signal associated with the issuance of a system control interrupt is likewise set, thereby enabling the computer system to recognize and manage the system event.
A difficulty arises when more than one signal that is associated with multiple system events are grouped into a single input to the status register of a General-Purpose Event Register Block. In the architecture of many computer systems, the recognition of system events will be routed through a Super I/O device or another device that provides a communications controller for several devices and peripherals in the computer system, including the drive bays, keyboard, and mouse of the computer system. The Super I/O or integrated I/O controller is coupled to the General-Purpose Event Register Block, which may reside in the I/O Controller Hub or similar device of the computer system. The integrated I/O controller typically has a single output that is coupled to the status register of the General-Purpose Event Register Block. As an example of such an architecture, a drive bay, a keyboard, and a mouse may each be coupled to the Super I/O or integrated I/O controller of the computer system. Thus, in this example, a system event associated with either the drive bay, keyboard, or mouse of the computer system will result in the integrated I/O controller setting an input bit in the status register of the General-Purpose Event Register Block. Because only a single signal is transmitted from the controller, the General-Purpose Event must be shared among all of the power events, and the power and configuration management system is not able to identify for the operating system the source of the system event. Thus, the integrated I/O controller can identify only that a non-unique or generic power or configuration event has occurred in one of the devices that reports power events to the integrated I/O controller. Because of the difficulty of differentiating among multiple system events coupled to a single integrated I/O controller, the power and configuration management system and the operating system of the computer system cannot operate in a manner that depends upon the differentiation of these system events. As an example, because the operating system cannot differentiate between the activation of the keyboard and the activation of a mouse, a system control interrupt is issued whenever a keyboard or mouse is activate, regardless of the preferences of the power and configuration management system for separately managing keyboard or mouse activations in a low power state.
In addition, the use of a single signal from the integrated I/O controller to the General-Purpose Event Register Block prevents the power management system and the operating system from distinguishing between power events, such as a wake event caused by the activation of a device while the computer system is in a low power state, and a configuration event, such as a run-time event, like the hot-plugging of a device in the computer system. From the perspective of the power management system and the operating system, both power events and configuration events are indistinguishable and the same response, the issuance of a system control interrupt, is indiscriminately employed for both types of events. As just one example of the difficulties caused by this architecture, the enable bit of the General-Purpose Event Register Block will frequently be disabled during those periods when the computer system is not in a lower power state. Because the enable bit is not set during these periods, any run-time events that occur during the period that the computer system is awake will not be recognized by the computer system.
One solution for differentiating between system events in the power and configuration management system is to include a separate input to the I/O Controller Hub for each system event. This solution would involve an architecture in which a signal associated with each system event is coupled to an input pin of the I/O Controller Hub. One difficulty of this architecture is that the number of available input pins on the I/O Controller Hub is scarce and not limitless. Dedicating an input pin to each power event to be tracked by the power management system and the operating system may not be a resourceful or practical use of the available pins of the I/O Controller Hub.